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5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller ADP3166*
FEATURES Selectable 2-, 3- or 4-Phase Operation at up to 1 MHz per Phase Differential Sensing Error 1% over Temperature Logic-Level PWM Outputs for Interface to External High Power Drivers Active Current Balancing between All Output Phases Built-in Power Good Blanking Supports On-the-Fly VID Code Changes 5-Bit Digitally Programmable 0.8 V to 1.55 V Output Short-Circuit Protection with Programmable Latch-Off Delay Overvoltage Protection Crowbar Logic Output APPLICATIONS Desktop PC Power Supplies Next-Generation AMD Processors VRM Modules GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
VCC 28 RAMPADJ RT 14 13
ADP3166
EN 11 UVLO SHUTDOWN AND BIAS OSCILLATOR + GND 19 CROWBAR 6 CSREF 2.1V DAC + 300mV CSREF + - DAC - 300mV 23 SW1 PWRGD 10 DELAY 22 SW2 21 SW3 ILIMIT 15 EN CURRENT LIMIT CIRCUIT - + 20 SW4 17 CSSUM 16 CSREF 18 CSCOMP SOFT START COMP 9 - + + - 8 FB + - + - CURRENT BALANCING CIRCUIT + -
CMP
-
CMP
SET RESET
EN 27 PWM1
+ -
CMP
RESET 2-, 3- , 4-PHASE DRIVER LOGIC RESET
26 PWM2
25 PWM3
+ -
CMP
RESET
24 PWM4
CROWBAR
CURRENT LIMIT
The ADP3166 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance AMD processors. It uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.8 V and 1.55 V. The ADP3166 also uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3166 includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3166 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU. ADP3166 is specified over the commercial temperature range of 0C to 85C and is available in a 28-lead TSSOP package.
DELAY 12
PRECISION REFERENCE 7 FBRTN 1 VID4 2 VID3
VID DAC 3 VID2 4 VID1 5 VID0
*Patent pending
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADP3166-SPECIFICATIONS1 (V
Parameter ERROR AMPLIFIER Accuracy 0.8 V Output 1.175 V Output 1.55 V Output Line Regulation Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-Up Resistance Internal Pull-Up Voltage VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation VFB IFB IFBRTN IO(ERR) GBW(ERR) Symbol VFB
CC
= 12 V, FBRTN = GND, TA = 0 C to 85 C, unless otherwise noted.)
Min Typ Max Unit
Conditions
Referenced to FBRTN, CSSUM = CSCOMP, 0.792 0.800 0.808 See Test Circuit 1 Referenced to FBRTN, CSSUM = CSCOMP, 1.163 1.175 1.187 See Test Circuit 1 Referenced to FBRTN, CSSUM = CSCOMP, 1.535 1.55 1.566 See Test Circuit 1 VCC = 10 V to 14 V 0.05 -13 -15.5 -17 100 200 FB forced to VOUT - 3% 500 COMP = FB 20 CCOMP = 10 pF 50 0.8 2 VID(X) = 0 V 100 2.0 400 400 20 120 2.4 26 2.65
V V V % A A A MHz V/s V V A k V ns ns
VIL(VID) VIH(VID) IVID RVID
VID code change to FB change VID code change to 11111 to PWM going low fOSC fPHASE VRT VRAMPADJ IRAMPADJ VOS(CSA) IBIAS(CSA) GBWCSA VFB ICSCOMP VSW(X)CM RSW(X) ISW(X) ISW(X)
Output Voltage Timing Resistor Value RAMPADJ Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Positioning Accuracy Output Voltage Range Output Current CURRENT BALANCE CIRCUIT Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR Output Voltage Normal Mode In Shutdown Output Current, Normal Mode Maximum Output Current Current Limit Threshold Voltage Current Limit Setting Ratio Latch-Off Delay Threshold Latch-Off Delay Time
TA = 25C, RT = 250 k, 4-phase TA = 25C, RT = 115 k, 4-phase2 TA = 25C, RT = 75 k, 4-phase2 RT = 100 k to GND RAMPADJ - FB
0.25 160
1.9 -50 0 -3
200 400 600 2.0
4 240
2.1 500 +50 50 +3 100
MHz kHz kHz kHz V k mV A mV nA MHz V/s V mV V A mV k A %
CSSUM - CSREF, see Test Circuit 2
CCSCOMP = 10 pF CSSUM and CSREF See Test Circuit 3 ICSCOMP = 100 A
20 20 50 0 -76 0.05 -80 500 -600 24 5 -5
3 -84 3.3
SW(X) = 0 V SW(X) = 0 V SW(X) = 0 V
30 7
+200 36 9 +5
VILIMIT(NM) VILIMIT(SD) IILIMIT(NM) VCL VSET(DLY) tSET(DLY)
EN > 2 V EN < 0.8 V, IILIMIT = -100 A EN > 2 V, RILIMIT = 250 k EN > 2 V VCSREF - VCSCOMP, RILIMIT = 250 k VCL/IILIMIT In current limit RDELAY = 250 k, CDELAY = 4.7 nF
2.9
3 12
3.1 400
60 105 1.7
125 10.4 1.8 600
145 1.9
V mV A A mV mV/A V s
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ADP3166
Parameter SOFT START Output Current, Soft Start Mode Soft Start Delay Time ENABLE INPUT Input Low Voltage Input High Voltage Input Current POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Off-State Leakage Current Delay Time VID Code Changing VID Code Static CROWBAR COMPARATOR Crowbar Trip Point Crowbar Reset Point Crowbar Response Time Overvoltage to PWM Low Overvoltage to CRWBR High Output Voltage Low Output Voltage High PWM OUTPUTS Output Voltage Low Output Voltage High SUPPLY DC Supply Current UVLO Threshold Voltage UVLO Hysteresis Symbol IDELAY(SS) tDELAY(SS) Conditions During start-up, DELAY < 2.8 V RDELAY = 250 k, CDELAY = 4.7 nF VID Code = 01111 Min 15 Typ 20 350 Max 25 Unit A s
VIL(EN) VIH(EN)
0.8 2 -1 Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = 4 mA VCSREF = VDAC -200 200 -300 300 150 +1 -400 400 400 50
V V A mV mV mV A s ns
VPWRGD(UV) VPWRGD(OV) VOL(PWRGD)
100
250 400 2.1 400 400 400 100 5.0 160 5.0 7 6.9 0.9 2.2 500
VCROWBAR tCROWBAR VOL(CROWBAR) ICROWBAR(SINK) = 100 A VOH(CROWBAR) ICROWBAR(SOURCE) = 100 A VOL(PWM) VOH(PWM) ICC VUVLO IPWM(SINK) = 400 A IPWM(SOURCE) = 400 A
2.0 300
V mV ns ns mV V mV V mA V V
500
4.0
500
4.0
VCC rising
6.5 0.7
10 7.3 1.1
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2 Guaranteed by design, not tested in production. Specifications subject to change without notice.
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ADP3166
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +15 V FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VID0 to VID4, EN, DELAY, ILIMIT, CSCOMP, RT, COMP, CROWBAR, PWM1 to PWM4 . . . . . . . . . -0.3 V to +5.5 V SW1 to SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . -5 V to +25 V All Other Inputs and Outputs . . . . . . . -0.3 V to VCC + 0.3 V Operating Ambient Temperature Range . . . . . . . 0C to 85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
ORDERING GUIDE
Model ADP3166JRU-REEL7 ADP3166JRU-REEL
Temperature Range 0C to 85C 0C to 85C
Package Options RU-28 (TSSOP-28) RU-28 (TSSOP-28)
Quantity per Reel 1000 2500
5.3 TA = 25 C 4-PHASE OPERATION 5.2
4
MASTER CLOCK FREQUENCY - MHz
0 0.5 1.0 1.5 2.0 2.5 3.0 MASTER CLOCK FREQUENCY - MHz 3.5 4.0
SUPPLY CURRENT - mA
3
5.1
5.0
2
4.9
4.8
1
4.7
4.6
0 0 50 100 150 200 RT VALUE - k 250 300
TPC 1. Supply Current vs. Master Clock Frequency
TPC 2. Master Clock Frequency vs. RT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3166 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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ADP3166
ADP3166
1 2 3
VID4 VID3 VID2 VID1 VID0 CROWBAR FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 SW1 23 SW2 22 SW3 21
+ 1F
12V 100nF
12V
28
ADP3166
VCC
5-BIT CODE
4 5 6 7 8 9
FB
8
10k COMP
9
200k
18
CSCOMP
200k
1k
10
17
GND 19 CSCOMP 18 20k 100nF CSSUM 17 CSREF 16 ILIMIT 15 250k
80mV
CSREF
16
1.25V
11 12
1V
+ -
19
GND
4.7nF
250k
VFB = FB - VVID
13 14
Test Circuit 1. Closed-Loop Output Voltage Accuracy
Test Circuit 3. Positioning Voltage Test Circuit
ADP3166
VCC 12V
28
CSCOMP
18
100nF 39k CSSUM
17
1k
16
CSREF
+ -
19
1V
GND
VOS = CSCOMP - 1V 40
Test Circuit 2. Positioning Amplifier VOS Test Circuit
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-5-
+
+ -
-
SW4 20
CSSUM
+
-
ADP3166
PIN CONFIGURATION RU-28
VID4 1 VID3 2 VID2 3 VID1 4 VID0 5 CROWBAR 6 FBRTN 7 FB 8 COMP 9 PWRGD 10 EN 11 DELAY 12 RT 13 RAMPADJ 14
28 27 26
VCC PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 GND CSCOMP CSSUM CSREF ILIMIT
ADP3166
TOP VIEW (Not to Scale)
25 24 23 22 21 20 19 18 17 16 15
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic 1-5 VID4-VID0
Function Voltage Identification DAC Inputs. These five pins are pulled up to an internal reference, providing a logic 1 if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.8 V to 1.55 V. Leaving VID4 through VID0 open results in the ADP3166 going into a "No CPU" mode, shutting off its PWM outputs. Crowbar Output. This logic-level output can be used to control an external device to short the 12 V supply to ground to protect the CPU from overvoltage if CSREF exceeds 2.1 V. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. A resistor between this pin and the output voltage sets the no-load offset point. Error Amplifier Output and Compensation Point. Power Good Output. Open-drain output that pulls to GND when the output voltage is outside of the proper operating range. Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs. Soft Start Delay and Current Limit Latch-Off Delay Setting Input. A resistor and capacitor connected between this pin and GND sets the soft start ramp-up time and the overcurrent latch-off delay time. Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Current Input. A resistor from the converter input voltage to this pin sets the internal PWM ramp. Current Limit Set Point/Enable Output. A resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3166 EN input is low, or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low. Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifiers and the Power Good and Crowbar functions. This pin should be connected to the common point of the output inductors. Current Sense Summing Node. Resistors from each switch node to this pin sum the average inductor currents together to measure the total output current. Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the slope of the load line and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be grounded.
6 7 8 9 10 11 12 13 14 15
CROWBAR FBRTN FB COMP PWRGD EN DELAY RT RAMPADJ ILIMIT
16
CSREF
17 18 19 20-23 24-27
CSSUM CSCOMP GND SW4-SW1
PWM4-PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3413 or ADP3418. Connecting the PWM3 and/or PWM 4 outputs to GND will cause that phase to turn off, allowing the ADP3166 to operate as a 2-, 3-, or 4-phase controller. VCC Supply Voltage for the Device. -6- REV. 0
28
ADP3166
THEORY OF OPERATION Table I. VID Code vs. Output Voltage
The ADP3166 combines a multimode, fixed frequency PWM control with multiphase logic outputs for use in 2-, 3-, and 4-phase synchronous buck CPU core supply power converters. The internal 5-bit VID DAC conforms to AMD's Hammer family power specifications. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling the high currents in a singlephase converter would place high thermal demands on the components in the system such as the inductors and MOSFETs. The multimode control of the ADP3166 ensures a stable, high performance topology for * * * * * * * * * Balancing currents and thermals between phases. High speed response at the lowest possible switching frequency and output decoupling. Minimizing thermal switching losses due to lower frequency operation. Tight load line regulation and accuracy. High current output from having up to 4-phase operation. Reduced output ripple utilizing multiphase cancellation. Immunity to board layout. Ease of use and design due to independent component selection. Flexibility in operation for tailoring design to low cost or high performance.
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOUT(NOM) (V) No CPU 0.800 0.825 0.850 0.875 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550
Number of Phases
The number of operational phases and their phase relationship are determined by internal circuitry that monitors the PWM outputs. Normally, the ADP3166 operates as a 4-phase PWM controller. Grounding the PWM 4 pin programs 3-phase operation, and grounding the PWM3 and PWM4 pins programs 2-phase operation. When the ADP3166 is enabled, the controller outputs a voltage on PWM3 and PWM4 that is approximately 550 mV. An internal comparator checks each pin's voltage versus a threshold of 400 mV. If the pin is grounded, it will be below the threshold and the phase will be disabled. The output impedance of the PWM pin is approximately 5 k. Any external pull-down resistance connected to the PWM pin should not be less than 25 k to ensure proper operation. The phase detection is made during the first two clock cycles of the internal oscillator. After this time, if the PWM output was not grounded, it will switch between 0 V and 5 V. If the PWM output was grounded, it will remain off. The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3418. Since each phase is monitored independently, operation approaching 100% duty cycle is possible. Also, more than one output can be on at a time for overlapping phases.
Master Clock Frequency
Output Voltage Differential Sensing
The ADP3166 combines differential sensing with a high accuracy VID DAC and reference and a low offset error amplifier to maintain a worst-case specification of 1% differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. FBRTN should be connected directly to the remote sense ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 100 A to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
Output Current Sensing
The clock frequency of the ADP3166 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in TPC 1. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, divide the master clock by 3 for the frequency of the remaining phases. If PWM3 and PWM4 are grounded, divide by 2. If all phases are in use, divide by 4. REV. 0 -7-
The ADP3166 provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning versus load current, and for current limit detection. Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low-side MOSFET.
ADP3166
This amplifier can be configured several ways depending on the objectives of the system: * * * Output inductor ESR sensing without thermistor for lowest cost Output inductor ESR sensing with thermistor for improved accuracy with tracking of inductor temperature Sense resistors for highest accuracy measurements EN is a logic low, the DELAY pin is held at ground. After the UVLO threshold is reached and EN is a logic high, the DELAY capacitor is charged up with an internal 20 A current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current. The soft start time depends on the value of VID DAC and CDLY, with a secondary effect from RDLY. Refer to the Applications section for detailed information on setting CDLY. When the PWRGD threshold is reached, the soft start cycle is stopped and the DELAY pin is pulled up to 3 V. This ensures that the output voltage is at the VID voltage when the PWRGD signals to the system that the output voltage is good. If EN is taken low or if VCC drops below UVLO, the DELAY capacitor is reset to ground to be ready for another soft start cycle.
Current Limit and Short-Circuit Protection
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. The current information is then given as the difference of CSREF - CSCOMP. This difference signal is used internally to offset the VID DAC for voltage positioning, and as a differential input for the current limit comparator. To provide the best accuracy for the sensing of current, the CSA has been designed to have a low offset input voltage. Also, the sensing gain is determined by external resistors so that it can be made extremely accurate.
Active Impedance Control Mode
The ADP3166 compares a programmable current limit set point to the voltage on the output of the current sense amplifier at the CSCOMP pin. The level of current limit is set with the resistor from the ILIMIT pin to ground. During normal operation, the voltage on ILIMIT is 3 V. The current through the external resistor is internally scaled to give a current limit threshold of 10.4 mV/A. If the difference in voltage between CSREF and CSCOMP drops below the current limit threshold, the internal current limit amplifier will control the internal COMP voltage to maintain the average output current at the limit. After the limit is reached, the 3 V pull-up on the DELAY pin is disconnected, and the external delay capacitor is discharged through the external resistor. A comparator monitors the DELAY voltage and shuts off the controller when the voltage drops below 1.8 V. The current limit latch-off delay time is therefore set by the RC time constant discharging from 3 V to 1.8 V. The Applications section discusses the selection of RDLY based on the CDLY that has been chosen. Because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.8 V threshold is reached, the controller will return to normal operation. The recovery characteristic depends on the state of PWRGD. If the output voltage is within the PWRGD window, the controller resumes normal operation. However, if short circuit has caused the output voltage to drop below the PWRGD threshold, then a soft start cycle is initiated. The latch-off function can be reset by either removing and reapplying VCC to the ADP3166, or by pulling the EN pin low for a short time. To disable the short-circuit latch-off function, the external resistor to ground should be left open, and a large (greater than 1 M) resistor should be connected from VCC to DELAY. This prevents the DELAY capacitor from discharging so the 1.8 V threshold is never reached. The resistor will have an impact on the soft start time because the current through it will add to the internal 20 A current source. During startup when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 2 V. This will limit the voltage drop across the low-side MOSFETs through the current balance circuitry.
For controlling the dynamic output voltage droop as a function of output current, a signal proportional to the total output current at the CSCOMP pin can be scaled to be equal to the droop impedance of the regulator times the output current. This droop voltage is then used to set the input control voltage to the system. The droop voltage is subtracted from the DAC reference input voltage directly to tell the error amplifier where the output voltage should be. This differs from previous implementations and allows enhanced feed-forward response.
Voltage Control Mode
A high gain-bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID 5-bit logic code according to the voltages listed in Table I. This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input (FB) is tied to the output sense location with a resistor, RB, and is used for sensing and controlling the output voltage at this point. A current source from the FB pin flowing through RB is used for setting the no-load offset voltage from the VID voltage. The no-load voltage will be positive with respect to the VID DAC. The main loop compensation is incorporated in the feedback network between FB and COMP.
Soft Start
The power-on ramp-up time of the output voltage is set with a capacitor and resistor in parallel from the DELAY pin to ground. The RC time constant also determines the current limit latch-off time, as explained in the following section. In UVLO or when
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ADP3166
Dynamic VID APPLICATION INFORMATION
The ADP3166 incorporates the ability to dynamically change the VID input while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID-OTF can occur under either light load or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be either positive or negative. When a VID input changes state, the ADP3166 detects the change and blanks the DAC for a minimum of 400 ns. This time is to prevent a false code due to logic skew while the six VID inputs are changing. Additionally, the first VID change initiates the PWRGD blanking function for a minimum of 100 s to prevent a false PWRGD event. Each VID change will reset the internal timer.
Power Good Monitoring
The design parameters for a typical AMD K8 compliant CPU application are as follows: * * * * * * * * * Input voltage (VIN) = 12 V VID setting voltage (VVID) = 1.500 V Duty cycle (D) = 0.125 Maximum static output voltage error ( VSERR) = 50 mV Maximum dynamic output voltage error ( VDERR) = 70 mV Error voltage allowed for controller and ripple ( VRERR) = 20 mV Maximum output current (IO) = 56 A Maximum output current step ( IO) = 24 A Static output droop resistance (RO) based on: a) No load output voltage set at upper output voltage limit. VONL = VVID + VSERR - VRERR = 1.530 V b) Full load output voltage set at lower output voltage limit. * * * VOFL = VVID - VSERR + VRERR = 1.470 V RO = (VONL - VOFL)/ (IO) = (1.530 V - 1.470 V)/(56A) = 1.1 m Dynamic output droop resistance (ROD) based on: a) Output current step to no load with output voltage set at upper output dynamic voltage limit. VONLD = VVID + VDERR - VRERR = 1.550 V b) Output voltage prior to load change (at IOUT = IO). * * * * VOL = VONL - ( IO RO)= 1.504 V ROD = (VONLD - VOL)/ ( IO) = (1.550 V - 1.504 V)/(24A) = 1.9 m Number of phases (n) = 3 Switching frequency per phase (fSW) = 330 kHz
The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified previously, based on the VID voltage setting. PWRGD will go low if the output voltage is outside of this specified range. PWRGD is blanked during a VID-OTF event for a period of 100 s to prevent false signals during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) and the CROWBAR logic output goes high when the output voltage exceeds the upper power good threshold. This crowbar action releases once the output voltage has fallen back within specifications if no other faults are present. The release threshold is approximately 400 mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short of the high-side MOSFET, this action current limits the input supply or blow its fuse, protecting the microprocessor from destruction. The CROWBAR output can be used to signal an external input crowbar or other protection circuit.
Output Enable and UVLO
Setting the Clock Frequency
The input VCC must be higher than the UVLO threshold and the EN pin must be higher than its logic threshold for the ADP3166 to begin switching. IF UVLO is less than the threshold or the EN pin is a logic low, the ADP3166 is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground. In the application circuit, the ILIMIT pin should be connected to the OD pins of the ADP3418 drivers. Because ILIMIT is grounded, this disables the drivers such that both DRVH and DRVL are grounded. This feature is important to prevent discharging of the output capacitors when the controller is shut off. If the driver outputs were not disabled, a negative voltage could be generated on the output due to the high current discharge of the output capacitors through the inductors.
The ADP3166 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. With n = 3 for three phases, a clock frequency of 990 kHz sets the switching frequency of each phase, fSW, to 330 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. Figure 1 shows that to achieve a 990 kHz oscillator frequency, the correct value for RT is 200 k. Alternatively, the value for RT can be calculated using
RT =
1
(n x f SW x 5.83 pF ) - 1.5 1 M
(1)
where 5.83 pF and 1.5 M are internal IC component values. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor.
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ADP3166
L1 1.6 H VIN 12V VIN RTN D1 1N4148WS 2200 F/16V 3 NICHICON PW SERIES + C1 + C6 C9 4.7 F
U2 C8 ADP3418 100nF
1 BST 2 IN 3 OD 4 VCC DRVH 8 SW 7 PGND 6 DRVL 5 Q3 IPD06N03L Q2 IPD06N03L 10 F 5MLCC AROUND SOCKET Q1 IPD12N03L L2 600nH/1.6m C10 4.7nF R1 2.2 820 F/2.5V 8 OSCON SERIES 12m ESR (EACH) + C21 + C28 VCC(CORE) RTN
D2 1N4148WS
VCC(CORE) 0.8V-1.55V 56A
C7 4.7 F
D3 1N4148WS
C12 U3 ADP3418 100nF 1 BST 2 IN 3 OD 4 VCC DRVH 8 SW 7 PGND 6 DRVL 5
C13 4.7 F Q4 IPD12N03L
L3 600nH/1.6m C14 4.7nF R2 2.2
C11 4.7 F Q6 IPD06N03L Q5 IPD06N03L D4 1N4148WS
U4 ADP3418
1 BST 2 IN 3 OD 4 VCC DRVH 8 SW 7 PGND 6 DRVL 5
C16 100nF
C17 4.7 F Q7 IPD12N03L
L4 600nH/1.6m C18 4.7nF R3 2.2
C15 4.7 F Q9 Q8 IPD06N03L IPD06N03L
RTH 100k , 5%
R4 10
C19 1F
+ C20 33 F RR 383k
U1 ADP3166
VCC 28 PWM1 27 PWM2 26 PWM3 25 PWM4 24 RSW1* SW1 23 RSW2* SW2 22 RSW3* SW3 21 SW4 20 GND 19 CSCOMP 18 CSSUM 17 CSREF 16 ILIMIT 15 RLIM 200k CCS2 RCS1 1.5nF 35.7k RPH3 147k RCS2 73.2k RPH2 147k RPH1 147k
1 VID4 2 VID3 3 VID2 FROM CPU 4 VID1 5 VID0 6 CROWBAR CB 680pF CFB 18pF POWER GOOD ENABLE RB 2.00k CA RA 680pF 7.32k 7 FBRTN 8 FB 9 COMP 10 PWRGD 11 EN 12 DELAY CDLY 39nF *SEE THEORY OF OPERATION SECTION FOR DESCRIPTION OF OPTIONAL RSW RESISTORS RDLY 390k 13 RT RT 200k 14 RAMPADJ
CCS1 2.2nF
Figure 1. 56 AMD K8 CPU Supply Circuit
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Soft Start and Current Limit Latch-Off Delay Times
Because the soft start and current limit latch-off delay functions share the DELAY pin, these two parameters must be considered together. The first step is to set CDLY for the soft start ramp. This ramp is generated with a 20 A internal current source. The value of RDLY will have a second order impact on the softstart time because it sinks part of the current source to ground. However, as long as RDLY is kept greater than 200 k, this effect is minor. The value for CDLY can be approximated using
If the ripple voltage is less than that designed for, the inductor can be made smaller until the ripple value is met. This will allow optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. A 600 nH inductor is a good choice for a starting point, and it gives a calculated ripple current of 6.6 A. The inductor should not saturate at the peak current of 22 A, and should be able to handle the sum of the power dissipation caused by the average current of 18.7 A in the winding and the core loss. Another important factor in the inductor design is the DCR, which is used for measuring the phase currents. A large DCR will cause excessive power losses, while too small a value will lead to increased measurement error. A good rule is to have the DCR be about 1 to 1 1/2 times the static droop resistance (RO). For our example, we are using an inductor with a DCR of 1.6 m.
Designing an Inductor
VVID tSS CDLY = 20 A - x 2 x RDLY VVID
(2)
where tSS is the desired soft start time. Assuming an RDLY of 390 k and a desired a soft start time of 3 ms, CDLY is 36 nF. The closest standard value for CCS is 39 nF. Once CDLY has been chosen, RDLY can be calculated for the current limit latch off time using 1.96 x tDLY RDLY = (3) CDLY If the result for RDLY is less than 200 k , then a smaller soft start time should be considered by recalculating the equation for CDLY or a longer latch-off time should be used. In no case should RDLY be less than 200 k. In this example, a delay time of 8 ms makes RDLY = 402 k. The closest standard 5% value is 390 k.
Inductor Selection
Once the inductance and DCR are known, the next step is either to design an inductor or to find a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled. Using 20% for the inductance and 8% for the DCR (at room temperature) are reasonable tolerances that most manufacturers can meet. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-M(R) from Magnetics, Inc. or Micrometals) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. The best choices for a core geometry are closed-loop types, such as pot cores, PQ, U, and E cores, or toroids. A good compromise between price and performance are cores with a toroidal shape. There are many useful references for quickly designing a power inductor, such as * * Magnetic Designer Software Intusoft (http://www.intusoft.com) Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-8
The choice of inductance for the inductor determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs but allows using smaller-size inductors and, for a specified peak-to-peak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. In any multiphase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current in the inductor. Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage:
VVID x (1 - D) IR = fSW x L
(4)
L
VVID x ROD x 1 - (n x D) fSW xVRIPPLE
(
)
(5)
Solving Equation 5 for a 10 mV p-p output ripple voltage yields
L 1.5 V x 1.9 m x (1 - 0.375) = 540 nH 330 kHz x 10 mV
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Selecting a Standard Inductor
The following companies can provide design consultation and deliver power inductors optimized for high power applications upon request. * Coilcraft (847)639-6400 http://www.coilcraft.com Coiltronics (561)752-5000 http://www.coiltronics.com Sumida Electric Company (510) 668-0660 http://www.sumida.com Vishay Intertechnology (402) 563-6866 http://www.vishay.com
It is best to have a dual location for CCS in the layout so standard values can be used in parallel to get as close to the value desired. For this example, choosing CCS to be a 1.5 nF and 2.2 nF in parallel is a good choice. For best accuracy, CCS should be a 10% capacitor. The closest standard 1% value for R PH(X) is 147 k .
Inductor DCR Temperature Correction
*
*
With the inductor's DCR being used as the sense element and copper wire being the source of the DCR, one needs to compensate for temperature changes of the inductor's winding. Fortunately, copper has a well known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite and equal percentage change in resistance to that of the wire, it will cancel the temperature variation of the inductor's DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2 (see Figure 2) are needed to linearize the NTC and produce the desired temperature tracking.
*
Output Droop Resistance
The design requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to the static output droop resistance (RO). The output current is measured by summing together the voltage across each inductor and then passing the signal through a lowpass filter. This summer-filter is the CS amplifier configured with resistors RPH(X) (summers) and RCS, and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors:
PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR OR LOW SIDE MOSFET RTH
TO SWITCH NODES
TO VOUT SENSE
RPH1
RPH2
RPH3
ADP3166
CSCOMP RCS1 18 CCS KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES RCS2
RO =
RCS x RL RPH(X)
L RL x RCS
(6) (7)
CSSUM
17
CCS =
CSREF
16
One has the flexibility of choosing either RCS or RPH(X). It is best to select RCS equal to 100 k, and then solve for RPH(X) by rearranging Equation 6. R RPH(X) = L x RCS RO
Figure 2. Temperature Compensation Circuit Values
RPH(X) =
1.6 m x 100 k = 145.5 k 1.1m
The following procedure and expressions will yield values to use for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value. 1. Select an NTC based on type and value. Since we do not have a value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. 2. Based on the type of NTC, find its relative resistance value at two temperatures. The temperatures to use that work well are 50C and 90C. We will call these resistance values A (A is RTH(50C)/RTH(25C)) and B (B is RTH(90C)/RTH(25C)). Note that the NTC's relative value is always 1 at 25C. 3. Next, find the relative value of RCS required for each of these temperatures. This is based on the percentage change needed, which we will initially make 0.39%/C. We will call these r1 (r1 is 1/(1 + TC (T1 - 25))) and r2 (r2 is 1/(1 + TC (T2 - 25))), where TC = 0.0039, T1 = 50C and T2 = 90C.
Next, use Equation 6 to solve for CCS:
CCS =
600 nH = 3.75 nF 1.6 m x 100 k
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4. Compute the relative values for RCS1, RCS2, and RTH using
RCS 2 = RCS1
RTH
1 A - 1 - RCS 2 r1 - RCS 2 1 = 1 1 - 1 - RCS 2 RCS1
( A - B) x r1 x r2 - A x (1 - B) x r2 + B x (1 - A) x r1 A x (1 - B) x r1 - B x (1 - A) x r2 - ( A - B) (1 - A) =
(8)
Combined ceramic values of 30 F to 100 F are recommended, usually made up of multiple ceramic capacitors. Select the number of ceramics and find the total ceramic capacitance (CZ). Next, there is an upper limit imposed on the total amount of bulk capacitance (CX) when one considers the VID on-the-fly voltage stepping of the output (voltage step VV in time tV with error of VERR) and a lower limit based on meeting the critical capacitance for load release for a given maximum load step IO:
L x IO C X ( MIN ) - CZ n x ROD xVVID
(12)
5. Calculate RTH = rTH RCS, then select the closest value of thermistor available. Also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: k= RTH ( ACTUAL) RTH (CALCULATED) (9)
CX ( MAX )
L x 2 n x K 2 x RO - CZ
2 VV V n x K x RO 1+ tV x VID x -1 VVID VV L
(13)
6. Finally, calculate values for RCS1 and RCS2 using the following: RCS1 = RCS x k x RCS1 (10) R = R x 1- k + k x R
CS 2 CS
(( ) (
CS 2
))
V where K -In ERR VV
To meet the conditions of these expressions and transient response, the ESR of the bulk capacitor bank (RX) should be less than or equal to the dynamic droop resistance, ROD. If the CX(MIN) is larger than CX(MAX), the system will not meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). For our example, a combination of MLCC capacitors (CZ = 50 F) was used. The VID on-the-fly step change is from 1.5 V to 0.8 V (making VV = 700 mV) in 100 s with a setting error of 3%. Solving for the bulk capacitance yields
600 nH x 24 A CX ( MIN ) - 50 F = 1.63 mF 3 x 1.9 m x 1.5 V
CX ( MAX ) 600 nH x 700 mV x 3 x 3.52 x 1.5V
For this example, RCS has been chosen to be 100 k, so we start with a thermistor value of 100 k. Looking through available 0603 size thermistors, we find a Vishay NTHS0603N01N1003JR NTC thermistor with A = 0.3602 and B = 0.09174. From these we compute RCS1 = 0.3796, RCS2 = 0.7195 and RTH = 1.0751. Solving for RTH yields 107.51 k, so we choose 100 k, making k = 0.9302. Finally, we find RCS1 and RCS2 to be 35.3 k and 73.9 k. Choosing the closest 1% resistor values yields a choice of 35.7 k and 73.2 k.
Output Offset
AMD's specification requires that at no load, the nominal output voltage of the regulator be offset to a higher value than the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB pin (IFB) and flowing through RB. The value of RB can be found using Equation 11:
VONL - VVID I FB 1.53 V - 1.5 V = 2.00 k RB = 15 A The closest standard 1% resistor value is 2.00 k. RB =
COUT Selection
(11)
2 100 ms x 1.5 V x 3 x 3.5 x 1.1m 1+ - 1 - 50 mF = 20.4 mF 700 mV x 600 nH
The required output decoupling for the regulator is typically recommended by AMD for various processors and platforms. One can also use some simple design guidelines to determine what is required. These guidelines are based on having both bulk and ceramic capacitors in the system. The first thing is to select the total amount of ceramic capacitance, which is based on the number and type of capacitor to be used. The best location for ceramics is inside the socket. Others can be placed along the outer edge of the socket as well.
where K = 3.5. Using eight 820 F OSCONs with a typical ESR of 12 m each yields CX = 6.56 mF with an RX = 1.5 m. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the initial high frequency transient spike. This is tested using LX 2 x C Z x ROD
2
LX 2 x 50 mF x 1.9 mW 2 = 361 pH
(14)
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In this example, LX is 375 pH for the eight OSCON capacitors, which basically satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of capacitors must be increased. One should note for this multimode control technique, allceramic designs can be used as long as the conditions of Equations 12, 13, and 14 are satisfied.
Power MOSFETs
takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET, where nMF is the total number of main MOSFETs: PS ( MF ) = 2 x fSW x VCC x IO n x RG x MF x C ISS nMF n (16)
For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3418) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE ~10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current, IO, determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3166, currents are balanced between phases, thus the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO):
Here, RG is the total gate resistance (2 for the ADP3418 and about 1 for typical high speed switching MOSFETs, making R G = 3 ) and C ISS is the input capacitance of the main MOSFET. It is interesting to note that adding more main MOSFETs (nMF) does not really help the switching loss per MOSFET since the additional gate capacitance slows down switching. The best thing to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by the following, where RDS(MF) is the on resistance of the MOSFET:
I 2 1 n x I 2 R PC ( MF ) = D x O + x x RDS ( MF ) (17) 12 nMF nMF
PSF
I 2 1 n x I 2 R = (1 - D) x O + x x RDS (SF ) (15) 12 nSF nSF
Typically, for main MOSFETs, one wants the highest speed (low CISS) device, but these usually have higher on resistance. One must select a device that meets the total power dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses. For our example, we have selected an Infineon IPD12N03L as the main MOSFET (three total; nMF = 3), with a CISS = 1460 pF (max) and RDS(MF) = 14 m (max at TJ = 120C) and an Infineon IPD06N03L as the synchronous MOSFET (six total; nSF = 6), with CISS = 2370 pF (max) and RDS(SF) = 8.4 m (max at TJ = 120C). The synchronous MOSFET CISS is less than 3000 pF, satisfying that requirement. Solving for the power dissipation per MOSFET at IO = 56 A and IR = 6.6 A yields 647 mW for each synchronous MOSFET and 1.26 W for each main MOSFET. These numbers work well considering there is usually more PCB area available for each main MOSFET versus each synchronous MOSFET. One last thing to look at is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following, where QGMF is the total gate charge for each main MOSFET and QGSF is the total gate charge for each synchronous MOSFET:
f PDRV = SW x (nMF x QGMF + nSF x QGSF ) + ICC xVCC (18) 2 x n
Knowing the maximum output current being designed for and the maximum allowed power dissipation, one can find the required RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an ambient temperature of 50C, a safe limit for PSF is 1 W to 1.5 W at 120C junction temperature. Thus, for our example (56 A maximum), we find RDS(SF) (per MOSFET) < 10 m. This RDS(SF) is also at a junction temperature of about 120C, so we need to make sure we account for this when making this selection. For our example, we selected two lower-side MOSFETs at 7 m each at room temperature, which gives 8.4 m at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and the feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch off the synchronous MOSFETs should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3418). The output impedance of the driver is about 2 and the typical MOSFET input gate resistances are about 1 to 2 , so a total gate capacitance of less than 6000 pF should be adhered to. Since there are two MOSFETs in parallel, we should limit the input capacitance for each synchronous MOSFET to 3000 pF. The high-side (main) MOSFET must be able to handle two main power dissipation components: conduction and switching losses. The switching loss is related to the amount of time it
Also shown is the standby dissipation factor (ICC VCC) for the driver. For the ADP3418, the maximum dissipation should be less than 400 mW. For our example, with ICC = 7 mA, QGMF = 22.8 nC and QGSF = 34.3 nC, we find 265 mW in each driver, which is below the 400 mW dissipation limit. See the ADP3418 data sheet for more details.
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Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. The following expression is used for determining the optimum value:
For values of RLIM greater than 500 k, the current limit may be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. For our example, choosing 75 A for ILIM, we find RLIM to be 378 k, for which we choose 374 k as the nearest 1% value. The per phase current limit described earlier has its limit determined by the following:
RR =
AR x L 3 x AD x RDS x CR
(19)
I PHLIM
0.2 x 600 nH = 381k RR = 3 x 5 x 4.2 mW x 5 pF
VCOMP(MAX) - VR - VBIAS I R - AD x RDS(MAX) 2
(23)
where AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain, RDS is the total low-side MOSFET on resistance, and CR is the internal ramp capacitor value. The closest standard 1% resistor value is 383 k. The internal ramp voltage magnitude can be calculated using VR = VR = AR x (1 - D) xVVID 0.2 x (1 - 0.125) x 1.5 V RR x CR x fSW (20) = 0.41 V
For the ADP3166, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.2 V, and the current balancing amplifier gain (AD) is 5. Using VR of 0.48 V, and RDS(MAX) of 4.2 m (low-side on resistance at 150C), we find a per phase limit of 74 A. This limit can be adjusted by changing the ramp voltage VR. But make sure not to set the per phase limit lower than the average per phase current (ILIM/n). There is also a per phase initial duty cycle limit determined by: DMAX = D x VCOMP ( MAX ) -VBIAS VRT (24)
383 k x 5 pF x 330 kHz
For this example, the maximum duty cycle is found to be 0.55. The size of the internal ramp can be made larger or smaller. If it is made larger, stability and transient response will improve, but thermal balance will degrade. Conversely, if the ramp is made smaller, thermal balance will improve at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 19 sets a ramp size that gives an optimal balance for good stability, transient response, and thermal balance.
COMP Pin Ramp Feedback Loop Compensation Design
There is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input. VRT = VR (RO + ROD ) x (1 - nD) 1 - n x fSW x CX x RO x ROD
Optimized compensation of the ADP3166 allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is optimized over the widest possible frequency range, including dc, and equal to the droop resistances (RO and ROD). With the output impedance, the output voltage will respond in proportion with the load current; this ensures the optimal output positioning and allows the minimization of the output decoupling. With the multimode feedback structure of the ADP3166, one needs to set the feedback compensation to make the converter's output impedance work in parallel with the output decoupling to meet this goal. There are several poles and zeros created by the output inductor and decoupling capacitors (output filter) that need to be compensated for.
(21)
For this example, the overall ramp signal is found to be 0.48 V.
Current Limit Set Point
To select the current limit set point, we need to find the resistor value for RLIM. The current limit threshold for the ADP3166 is set with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/A (ALIM). RLIM can be found using the following: RLIM = ALIM x VLIM I LIM x RO (22)
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The first step is to compute the time constants for all of the poles and zeros in the system:
Re = n x ROD + AD x RDS + RL x VRT ( RO + ROD ) x L x (1 - n x D) x VRT + VVID n x CX x RO x ROD x VVID
Re = 3 x 1.9 m + 5 x 4.2 m + Re = 36.0 m
Ta = C X x ROD - R' +
1.6 m x 0.48 V (1.1 m + 1.9 m) x 600 nH x (1 - 0.375) x 0.48 V + 1.5 V 3 x 6.56 mF x 1.1 m x 1.9 m x 1.5 V
(25)
(
)
LX R - R' x OD ROD RX 375 pH 1.9 m - 0.6 m x 1.5 m 1.5 m
Ta = 6.56 mF x (1.9 m - 0.6 m) + Ta = 8.70 s
(26)
Tb = RX + R' - ROD x CX Tb = (1.5 m + 0.6 m - 1.9 m) x 6.56 mF = 1.31 s
A x RDS VRT x L - D 2 x fSW Tc = VVID x Re 5 x 4.2 m 0.48V x 600 nH - 2 x 330 kHz Tc = = 5.05s 1.5 V x 36.0 m
(
)
(27)
(28)
Td = Td =
CX x C Z x ROD CX x (RO - R) + C Z x ROD 6.56 mF x 50 mF x 1.9 m2 = 137 ns 6.56 mF x (1.9 m - 0.6 m) + 50 mF x 1.9 m
(29)
2
where, for the ADP3166, R' is the PCB resistance from the bulk capacitors to the ceramics and where RDS is the total low-side MOSFET on resistance per phase. For this example, AD is 5, VRT equals 0.48 V, R' is approximately 0.6 m (assuming a 4-layer motherboard), and LX is 375 pH for the eight OSCON capacitors. A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. The expressions that follow are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure section). The compensation values can then be solved using the following:
C FB =
Td 137 ns = 18.7 pF = R A 7.33 k
(33)
Choosing the closest standard values for these components yields: CA = 680 pF, RA = 7.32 k, CB = 680 pF, and CFB = 18 pF. Figure 3 shows the typical transient response using the compensation values.
CIN Selection and Input Current di/dt Reduction
n x ROD x Ta Re x RB 3 x 1.9 m x 8.70 s CA = = 689 pF 36.0 m x 2.00 k CA =
CB = Tb 1.31 s = 655 pF = RB 2.00 k Tb 1.31 s = 655 pF = RB 2.00 k
In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n VOUT/VIN and an amplitude one-nth of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by ICRMS = D x IO x 1 -1 nxD
(30)
(31)
CB =
(34) 1 - 1 = 9.05 A 3 x .125 Note that the capacitor manufacturer's ripple current ratings are often based on only 2,000 hours of life. This makes it advisable ICRMS = 0.125 x 56 A x
(32)
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to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by three 2200 F, 16 V Nichicon capacitors with a ripple current rating of 3.5 A each. To reduce the input-current di/dt to below the recommended maximum of 0.1 A/s, an additional small inductor (L > 1 H @ 15 A) should be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source.
AC Loadline Setting
11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div. 13. Set the dynamic load for a transient step of about 24 A at 1 kHz with 50% duty cycle. 14. Measure the output waveform (it might be necessary to use a dc offset on scope to see the waveform). Try to use a vertical scale of 100 mV/div or finer. 15. The waveform should look something like Figure 3. Use the horizontal cursors to measure V ACDRP and VDCDRP as shown. DO NOT MEASURE THE UNDERSHOOT OR OVERSHOOT THAT HAPPENS IMMEDIATELY AFTER THE STEP.
(VNL -VFLCOLD ) RCS2( NEW ) = RCS2(OLD) x (VNL -VFLHOT )
TUNING PROCEDURE FOR ADP3166
(35)
1. 2.
Build a circuit based on compensation values computed from the design spreadsheet. Hook up the dc load to the circuit, turn it on, and verify its operation. Also check for jitter at no load and full load. Measure the output voltage at no load (VNL). Verify that it is within tolerance. Measure the output voltage at full load cold (VFLCOLD). Let the board set for a ~10 minutes at full load and measure output (VFLHOT). If there is a change of more than a few millivolts, adjust RCS1 and RCS2 using Equations 35 and 37. Repeat Step 4 until the cold and hot voltage measurements remain the same. Measure the output voltage from no load to full load using 5 A steps. Compute the loadline slope for each change and then average them to get the overall loadline slope (ROMEAS). If ROMEAS is off by more than 0.05 m from RO, use Equation 36 to adjust the RPH values: RPH ( NEW ) = RPH (OLD) ROMEAS RO (36)
Figure 3. AC Loadline Waveform
VACDRP VDCDRP
DC Loadline Setting
3. 4.
5. 6.
7.
16. If the VACDRP and VDCDRP are different by more than a few millivolts, use the following to adjust CCS. It might be necessary to parallel different values to get the right one since there are limited standard capacitor values available. (It is a good idea to have locations for two capacitors in the layout for this.) 17. Repeat Steps 11 to 13 and repeat adjustments if necessary. Once complete, do not change CCS for the rest of the procedure. 18. Set the dynamic load step to maximum step size (do not use a step size larger than needed), and verify that the output waveform is square (meaning VACDRP and VDCDRP are equal).
8. 9.
Repeat Steps 6 and 7 to check the loadline and repeat the adjustments if necessary. Once finished with dc loadline adjustment, do not change RPH, RCS1, RCS2, or RTH for the rest of the procedure.
10. Measure the output ripple at no load and at full load with a scope and make sure that it is within spec.
RCS 2( NEW ) = RCS1(OLD) x RTH
o
1 (25 C ) + RCS 2(OLD) - RCS2( NEW ) x RCS1(OLD) - RTH (25 C )
o
(
RCS1(OLD) + RTH
(25 C )
o
)
-
1 RTH
(25 C )
o
(37)
V CCS ( NEW ) = CCS (OLD) ACDRP V
(38)
DCDRP
REV. 0
-17-
ADP3166
Initial Transient Setting
19. With dynamic load still set at maximum step size, expand scope time scale to see 2 s/div to 5 s/div. The waveform may have two overshoots and one minor undershoot (see Figure 5). Here, VDROOP is the final desired static value.
12V CONNECTOR
SWITCH NODE PLANES
INPUT POWER PLANE
THERMISTOR VDROOP KEEP-OUT AREA OUTPUT POWER PLANE KEEP-OUT AREA VTRAN2 CPU SOCKET KEEP-OUT AREA
VTRAN1
Figure 4. Transient Setting Waveform
KEEP-OUT AREA
20. If the overshoots are larger than desired, try making the following adjustments in this order (Note: if these adjustments do not change the response, you are limited by the output decoupling). Check the output response each time a change is made as well as the switching nodes (to make sure it is still stable). a. Make the ramp resistor larger by 25% (RRAMP). b. For VTRAN1, increase CB or switching frequency. c. For VTRAN2, increase RA and decrease CA by 25%.
Figure 6. Layout Recommendations
General Recommendations
*
For good results, at least a four-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3166) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3166 for referencing the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. The components around the ADP3166 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. Refer to Figure 6 for more details on layout for the CSSUM node. The output capacitors should be connected as close as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop, described below. REV. 0
*
VTRANREL
VDROOP
*
*
Figure 5. Transient Setting Waveform
21. For load release (see Figure 5), if VTRANREL is larger than V TRAN1 (refer to Figure 4), there is not enough output capacitance. Either more capacitance is needed or it is necessary to make the inductor values smaller (if inductors are changed, it is necessary to start design over using the spreadsheet and this tuning guide).
LAYOUT AND COMPONENT PLACEMENT
*
The following guidelines are recommended for optimal performance of a switching regulator in a PC system. Key layout issues are illustrated in Figure 6.
*
* -18-
ADP3166
Power Circuitry
*
The switching power path should be routed on the PCB to encompass the shortest possible length to minimize radiated switching noise energy (i.e., EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noiserelated operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, the largest possible pad area should be used. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers extending fully under all the power components. The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connects to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Therefore the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the inductor nearest to the controller.
*
*
*
Signal Circuitry
*
*
REV. 0
-19-
ADP3166
OUTLINE DIMENSIONS 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28)
Dimensions shown in millimeters
9.80 9.70 9.60
28
15
4.50 4.40 4.30
1 14
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX
COPLANARITY 0.10
SEATING PLANE
0.20 0.09
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AE
-20-
REV. 0
C03589-0-4/03(0)

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